| dc.contributor.author | Vu, Tran Anh | |
| dc.date.accessioned | 2013-09-19T07:09:00Z | |
| dc.date.accessioned | 2018-05-23T02:10:03Z | |
| dc.date.available | 2013-09-19T07:09:00Z | |
| dc.date.available | 2018-05-23T02:10:03Z | |
| dc.date.issued | 2011 | |
| dc.identifier.uri | http://10.8.20.7:8080/xmlui/handle/123456789/528 | |
| dc.description.abstract | This project is an implementation of a VGA display generator, using FPGA device (ALTERA DE2 board). The goal of this project is to design a program that export picture to VGA monitor through SD card slot on DE2 board. The source code is designed using Verilog HDL language processed using Quartus II Design Software and Nios II, SoPC. The output is displayed using a standard VGA monitor with 640 by 480 pixels. | en_US |
| dc.description.sponsorship | Ph.D. Mai Linh | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | International University HCMC, Vietnam | en_US |
| dc.relation.ispartofseries | ;022000574 | |
| dc.subject | Field programmable gate arrays | en_US |
| dc.title | VGA display generation using FPGA altera DE2 board | en_US |
| dc.type | Thesis | en_US |
